Verilog HDL
Quick Reference Guide
based on the IEEE 1364-1995 standard
by Sutherland HDL, Inc.
Verilog Training Experts
www.sutherland-hdl.com
copyright 1997, All rights reserved.
You may download this
page for personal use.
You may not reproduce this
document or any portion thereof in any form! Verilog is a registered trademark
of Cadence Design Systems, San Jose, CA.
Table of Contents 1.0 Hierarchy Scopes
2.0 Concurrency
3.0 Reserved Keywords
4.0 Lexical Conventions
5.0 Module Definitions
6.0 Module Port Declarations
7.0 Data Type Declarations
7.1 Register Data
Types
7.2 Net Data Types
7.3 Other Data Types
8.0 Module Instances
9.0 Primitive Instances
10.0 Procedural Blocks
10.1 Timing Controls
10.2 Procedural
Assignments
10.3
Programming Statements
11.0 Operators
12.0 Continuous Assignments
13.0 Task Definitions
14.0 Function Definitions
15.0 Specify Blocks
16.0 User Defined
Primitives
17.0 Synthesis Constructs
18.0 System Tasks and
Functions
19.0 Compiler Directives